SC1100 Datasheet, PDF (304/348 Pages) National Semiconductor (TI) – Geode™ Information Appliance On a Chip

Electrical Specifications (Continued)
7.3.4 Sub-ISA Interface
All output timing is guaranteed for 50 pF load, unless otherwise specified.
The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011.
Symbol
t_RD1
t_RD2
t_RD3
t_RD4
t_RD5
t_RCU1
t_RCU2
t_RCU3
t_WR1
t_WR2
t_WR3
t_WR4
t_WR5
t_WCU1
t_WCU2
t_WCU3
t_RDYH
t_RDYA1
Table 7-16. Output Signals
Parameter
Bus
Width
Min
(Bits) Type (ns)
MEMR#/DOCR#/RD#/TRDE# Read
16
active pulse width FE to RE
M
225
MEMR#/DOCR#/RD#/TRDE# Read
16
active pulse width FE to RE
M
105
IOR#/RD#/TRDE# Read active pulse 16
width FE to RE
I/O
160
IOR#/MEMR#/DOCR#/RD#/TRDE#
Read active pulse width FE to RE
8
M, I/O 520
IOR#/MEMR#/DOCR#/RD#/TRDE#
Read active pulse width FE to RE
8
M, I/O 160
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
16
M
103
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
8
M
163
IOR#/RD#/TRDE# inactive pulse
width
8, 16
I/O
163
MEMW#/WR# Write active pulse
width FE to RE
16
M
225
MEMW#/DOCW#/WR# Write active
16
pulse width FE to RE
M
105
IOW#/WR# Write active pulse width
16
I/O
160
FE to RE
IOW#/MEMW#/DOCW#/WR# Write
active pulse width FE to RE
8
M, I/O 520
IOW#/MEMW#/DOCW#/WR# Write
active pulse width FE to RE
8
M, I/O 160
MEMW#/WR#/DOCW# inactive pulse 16
width
M
103
MEMW#/WR#/DOCW# inactive pulse
8
width
M
163
IOW#/WR# inactive pulse width
8, 16
I/O
163
IOR#/MEMR#/RD#/DOCR#/IOW#/
MEMW#/WR#/DOCW# Hold after
IOCHRDY RE
8, 16 M, I/O 120
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
16 M, I/O
Max
(ns) Figure Comments
7-17 Standard
7-17 Zero wait state
7-17 Standard
7-17 Standard
7-17 Zero wait state
7-17
7-17
7-17
7-18 Standard
7-18 Zero wait state
7-18 Standard
7-18 Standard
7-18 Zero wait state
7-18
7-18
7-18
7-17
7-18
78
7-17
7-18
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