SC1100 Datasheet, PDF (15/348 Pages) National Semiconductor (TI) – Geode™ Information Appliance On a Chip

Architecture Overview (Continued)
1.4.1.1 Power-On Reset
Power-on reset is triggered by assertion of the POR# sig-
nal. Upon power-on reset, the following things happen:
• Strap pins are sampled.
• PLL4, FMUL3, PLL5 are reset, disabling their output.
When the POR# signal is negated, FMUL3 performs
coarse locking of clocks, after which each FMUL outputs
its clock. FMUL3 is the last clock generator to output a
clock. See Section 3.5 "Clock Generators and PLLs" on
page 59.
• Certain WATCHDOG and High Resolution timer register
bits are cleared.
1.4.1.2 System Reset
System reset causes signal PCIRST# to be issued, thus
triggering reset of all PCI and LPC agents. A system reset
is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 3.3.2
"WATCHDOG Registers" on page 56).
• Software initiated system reset.
Revision 1.1
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