SC1100 Datasheet, PDF (266/348 Pages) National Semiconductor (TI) – Geode™ Information Appliance On a Chip

Core Logic Module (Continued)
Table 5-43. DMA Channel Control Registers (Continued)
Bit Description
2
Channel 2 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
1
Channel 1 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
0
Channel 0 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
Write
7
6
5
4
3
2
1:0
DACK Sense.
0: Active high.
1: Active low.
DREQ Sense.
0: Active high.
1: Active low.
Write Selection.
0: Late write.
1: Extended write.
Priority Mode.
0: Fixed.
1: Rotating.
Timing Mode.
0: Normal.
1: Compressed.
Channels 3:0.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
DMA Command Register, Channels 3:0
I/O Port 009h
Software DMA Request Register, Channels 3:0 (W)
7:3 Reserved. Must be set to 0.
2
Request Type.
0: Reset.
1: Set.
1:0 Channel Number Request Select
00: Channel 0.
01: Channel 1.
10: Channel 2.
11: Channel 3.
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