SC1100 Datasheet, PDF (130/348 Pages) National Semiconductor (TI) – Geode™ Information Appliance On a Chip

Core Logic Module (Continued)
5.2.6.3 Programmable Interrupt Controller
The Core Logic module contains two 8259A-equivalent
programmable interrupt controllers, with eight interrupt
request lines each, for a total of 16 interrupts. The two con-
trollers are cascaded internally, and two of the interrupt
request inputs are connected to the internal circuitry. This
allows a total of 13 externally available interrupt requests.
See Figure 5-9.
Each Core Logic IRQ signal can be individually selected as
edge- or level-sensitive. The four PCI interrupt signals may
be routed internally to any PIC IRQ.
.
8254 Timer 0
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IR0
IR1
IR2
IR3
IRQ5
IRQ6
IRQ7
IR4
IR5
IR6
IR7
Internal
INTR
RTC_IRQ#
FPU
IRQ8#
IRQ9
IRQ10
IRQ11
IRQ12
IR0
IR1
IR2
IR3
IRQ13
IRQ14
IRQ15
IR4
IR5
IR6
IR7
Table 5-4. PIC Interrupt Mapping
Master
IRQ
Mapping
IRQ0
IRQ2
IRQ8#
IRQ13
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ1
Connected to the OUT0 (system timer) of
the internal 8254 PIT.
Connected to the slave’s INTR for a cas-
caded configuration.
Connected to internal real-time clock.
Connected to the FPU interface of the
GX1 module.
Interrupts available to other functions
Figure 5-8. PIC Interrupt Controllers
Two interrupts are available externally depending upon
selected ball multiplexing:
1) IRQ15 (ball AF19, muxed with GPIO11+RI#),
2) IRQ14 (ball AC6)
More of the IRQs are available through the use of SERIRQ
(ball A24, muxed with GPIO39) function. See Table 5-4.
The Core Logic module allows PCI interrupt signals INTA#
(ball AD26), INTB# (ball W24), INTC# (ball Y24, muxed
with GPIO19) and INTD# (ball V24) to be routed internally
to any IRQ signal. The routing can be modified through
Core Logic module’s configuration registers. If this is done,
the IRQ input must be configured to be level- rather than
edge-sensitive. IRQ inputs may be individually pro-
grammed to be active low, level-sensitive with the Interrupt
Sensitivity configuration registers at I/O address space
4D0h and 4D1h. PCI interrupt configuration is discussed in
further detail in “PCI Compatible Interrupts” on page 131.
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