SC1100 Datasheet, PDF (125/348 Pages) National Semiconductor (TI) – Geode™ Information Appliance On a Chip

Core Logic Module (Continued)
5.2.5.5 ISA DMA
DMA transfers occur between ISA I/O peripherals and sys-
tem memory (i.e., not available externally). The data width
can be either 8 or 16 bits. Out of the seven DMA channels
available, four are used for 8-bit transfers while the remain-
ing three are used for 16-bit transfers. One byte or WORD
is transferred in each DMA cycle.
Note: The Core Logic module does not support DMA
transfers to ISA memory.
The ISA DMA device initiates a DMA request by asserting
one of the DRQ[7:5, 3:0] signals. When the Core Logic
module receives this request, it sends a bus grant request
to the PCI arbiter. After the PCI bus has been granted, the
respective DACK# is driven active.
The Core Logic module generates PCI memory read or
write cycles in response to a DMA cycle. Figure 5-4 and
Figure 5-5 are examples of DMA memory read and mem-
ory write cycles. Upon detection of the DMA controller’s
MEMR# or MEMW# active, the Core Logic module starts
the PCI cycle, asserts FRAME#, and negates an internal
IOCHRDY. This assures the DMA cycle does not complete
before the PCI cycle has provided or accepted the data.
IOCHRDY is internally asserted when IRDY# and TRDY#
are sampled active.
PCICLK
ISACLK
MEMR#
IOW#
SD[15:0]
IOCHRDY
FRAME#
AD[31:0]
IRDY#
TRDY#
Figure 5-4. ISA DMA Read from PCI Memory
PCICLK
ISACLK
MEMW#
IOR#
SD[15:0]
IOCHRDY
FRAME#
AD[31:0]
IRDY#
TRDY#
Figure 5-5. ISA DMA Write to PCI Memory
Revision 1.1
125
www.national.com