DS10CP154_1 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4X4 LVDS Crosspoint Switch

Pin Descriptions
Pin Name
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
EN_smb
S00/SCL,
S01/SDA
S10/ADDR0,
S11/ADDR1
S20/ADDR2,
S21/ADDR3
S30, S31
PWDN
NC
VDD
GND
Pin
Number
1, 2,
4, 5,
6, 7,
9, 10
29, 28,
27, 26,
24, 23,
22, 21
17
I/O, Type
I, LVDS
O, LVDS
I, LVCMOS
37,
I/O, LVCMOS
36
35,
I/O, LVCMOS
34
33,
I/O, LVCMOS
32
13, 14 I, LVCMOS
38
I, LVCMOS
11, 12,
18, 19,
20, 31,
39, 40
3, 8,
Power
15,25, 30
16, DAP Power
Pin Description
Inverting and non-inverting high speed LVDS input pins.
Inverting and non-inverting high speed LVDS output pins.
System Management Bus (SMBus) mode enable pin. The pin has
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
For EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-
functional and should be tied to either logic [0] or [1].
For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
No connect pins. May be left floating.
Power supply pins.
Ground pin and pad (DAP - die attach pad).
3
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