DS10CP154_1 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4X4 LVDS Crosspoint Switch

CONTROL REGISTER
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control
via the SMBus. The following table shows the register mapping.
Bit Default Bit Name
D[3:0] 1111
PWDNn
D[4] x
D[5] x
D[6] 0
n/a
n/a
EN_LOS
D[7] 0
SoftPWDN
Access
R/W
R/W
R/W
R/W
R/W
Description
Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
Undefined.
Undefined.
Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
PWDN
0
0
1
1
SoftPWDN
0
1
0
1
TABLE 8. DS10CP154 Power Modes Truth Table
PWDNn
x
x
x
x
DS25CP104 Power Mode
Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS REGISTER
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit Default Bit Name
D[0] 0
LOS0
D[1] 0
LOS1
D[2] 0
LOS2
D[3] 0
LOS3
D[7:4] 0000
Reserved
Access
RO
RO
RO
RO
RO
Description
Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
Reserved for future use. Returns undefined value when read.
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