OPA2830 Datasheet, PDF (29/43 Pages) National Semiconductor (TI) – Dual, Low-Power, Single-Supply, Wideband OPERATIONAL AMPLIFIER

OPA2830
www.ti.com.................................................................................................................................................. SBOS309D – AUGUST 2004 – REVISED AUGUST 2008
Frequency response in a gain of +2 may be modified
to achieve exceptional flatness simply by increasing
the noise gain to 3. One way to do this, without
affecting the +2 signal gain, is to add an 2.55kΩ
resistor across the two inputs, as shown in Figure 77.
A similar technique may be used to reduce peaking in
unity-gain (voltage follower) applications. For
example, by using a 750Ω feedback resistor along
with a 750Ω resistor across the two op amp inputs,
the voltage follower response will be similar to the
gain of +2 response of Figure 71. Further reducing
the value of the resistor across the op amp inputs will
further dampen the frequency response due to
increased noise gain. The OPA2830 exhibits minimal
bandwidth reduction going to single-supply (+5V)
operation as compared with ±5V. This minimal
reduction is because the internal bias control circuitry
retains nearly constant quiescent current as the total
supply voltage between the supply pins is changed.
INVERTING AMPLIFIER OPERATION
All of the familiar op amp application circuits are
available with the OPA2830 to the designer. See
Figure 84 for a typical inverting configuration where
the I/O impedances and signal gain from Figure 70
are retained in an inverting circuit configuration.
Inverting operation is one of the more common
requirements and offers several performance
benefits. It also allows the input to be biased at V_S/2
without any headroom issues. The output voltage can
be independently moved to be within the output
voltage range with coupling capacitors, or bias
adjustment resistors.
+5V
0.1µF
2R_T
1.5kΩ
2R_T
1.5kΩ
+
0.1µF
6.8µF
1/2
OPA2830
150Ω
+V_S
2
50Ω Source
R_G
0.1µF ₃₇₄Ω
R_M
57.6Ω
R_F
750Ω
Figure 84. AC-Coupled, G = –2 Example Circuit
signal channel input impedance. If input impedance
matching is desired (which is beneficial whenever the
signal is coupled through a cable, twisted pair, long
PC board trace, or other transmission line conductor),
R_G may be set equal to the required termination value
and R_F adjusted to give the desired gain. This is the
simplest approach and results in optimum bandwidth
and noise performance.
However, at low inverting gains, the resulting
feedback resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting R_G to 50Ω for input matching eliminates the
need for R_M but requires a 100Ω feedback resistor.
This configuration has the interesting advantage of
the noise gain becoming equal to 2 for a 50Ω source
impedance—the same as the noninverting circuits
considered above. The amplifier output will now see
the 100Ω feedback resistor in parallel with the
external load. In general, the feedback resistor should
be limited to the 200Ω to 1.5kΩ range. In this case, it
is preferable to increase both the R_F and R_G values,
as shown in Figure 84, and then achieve the input
matching impedance with a third resistor (R_M) to
ground. The total input impedance becomes the
parallel combination of R_G and R_M.
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For the example
in Figure 84, the R_M value combines in parallel with
the external 50Ω source impedance (at high
frequencies), yielding an effective driving impedance
of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in
series with R_G for calculating the noise gain. The
resulting noise gain is 2.87 for Figure 84, as opposed
to only 2 if R_M could be eliminated as discussed
above. The bandwidth will therefore be lower for the
gain of –2 circuit of Figure 84 (NG = +2.87) than for
the gain of +2 circuit of Figure 70.
The third important consideration in inverting amplifier
design is setting the bias current cancellation
resistors on the noninverting input (a parallel
combination of R_T = 750Ω). If this resistor is set equal
to the total DC resistance looking out of the inverting
node, the output DC error, due to the input bias
currents, will be reduced to (Input Offset Current)
times R_F. With the DC blocking capacitor in series
with R_G, the DC source impedance looking out of the
inverting mode is simply R_F = 750Ω for Figure 84. To
reduce the additional high-frequency noise introduced
by this resistor and power-supply feed-through, R_T is
bypassed with a capacitor.
In the inverting configuration, three key design
considerations must be noted. The first consideration
is that the gain resistor (R_G) becomes part of the
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