COPCH823CJ Datasheet, PDF (19/32 Pages) National Semiconductor (TI) – 8-bit Microcontroller with with Multi-Input Wake Up and Brown Detecter

Control Registers
CNTRL1 REGISTER (ADDRESS 00EE)
The Timer and MICROWIRE control register contains the
following bits
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 e 2 01 e 4 1x e 8)
IEDG
External interrupt edge polarity select
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
TRUN
Used to start and stop the timer counter
(1 e run 0 e stop)
TC1
Timer T1 Mode Control Bit
TC2
Timer T1 Mode Control Bit
TC3
Timer T1 Mode Control Bit
Bit 7
Bit 0
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
PSW REGISTER (ADDRESS 00EF)
The PSW register contains the following select bits
GIE Global interrupt enable (enables interrupts)
ENI External interrupt enable
BUSY MICROWIRE busy shifting flag
PND External interrupt pending
ENTI Timer T1 interrupt enable
TPND Timer T1 interrupt pending
(timer Underflow or capture edge)
C
Carry Flip Flop
HC Half-Carry Flip Flop
Bit 7
HC
Bit 0
C TPND ENTI IPND BUSY ENI GIE
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag The flag values depend upon the in-
struction For example after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved However instructions like SET C
and RESET C will set and clear both the carry flags Table
XIII lists the instructions that effect the HC and the C flags
TABLE XIII Instructions Effecting HC and C Flags
Instr
HC Flag
C Flag
ADC
Depends on Operands Depends on Operands
SUBC Depends on Operands Depends on Operands
SET C Set
Set
RESET C Set
Set
RRC
Depends on Operands Depends on Operands
CNTRL2 REGISTER (ADDRESS 00CC)
Bit 7
Bit 0
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF
unused
RW RW RW RW RO RW RO
MC3 Modulator Timer Control Bit
MC2 Modulator Timer Control Bit
MC1 Modulator Timer Control Bit
CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)
WDREG REGISTER (ADDRESS 00CD)
WDREN WATCHDOG Reset Enable Bit (Write Once Only)
Bit 7
UNUSED
Bit 0
WDREN
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