COPCH823CJ Datasheet, PDF (14/32 Pages) National Semiconductor (TI) – 8-bit Microcontroller with with Multi-Input Wake Up and Brown Detecter

Functional Description (Continued)
CONTROL STATUS BITS
WDUDF WATCHDOG Timer Underflow Bit
This bit resides in the CNTRL2 Register The bit is set when
the WATCHDOG timer underflows The underflow resets
the device if the WATCHDOG reset enable bit is set
(WDREN e 1) Otherwise WDUDF can be used as the tim-
er underflow flag The bit is cleared upon Brown-Out reset
external reset load to the 8-bit counter or going into the
HALT mode It is a read only bit
WDREN WD Reset Enable
WDREN bit resides in a separate register (bit 0 of WDREG)
This bit enables the WATCHDOG timer to generate a reset
The bit is cleared upon Brown Out reset or external reset
The bit under software control can be written to only once
(once written to the hardware does not allow the bit to be
changed during program execution)
WDREN e 1 WATCHDOG reset is enabled
WDREN e 0 WATCHDOG reset is disabled
Table VI shows the impact of Brown Out Reset WATCH-
DOG Reset and External Reset on the Control Status bits
FIGURE 12 WATCHDOG Timer Block Diagram
TL DD 11208 – 15
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