COPCH823CJ Datasheet, PDF (18/32 Pages) National Semiconductor (TI) – 8-bit Microcontroller with with Multi-Input Wake Up and Brown Detecter

Multi-Input Wakeup (Continued)
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FIGURE 16 Multi-Input Wakeup Logic
INTERRUPTS
The device has a sophisticated interrupt structure to allow
easy interface to the real world There are three possible
interrupt sources as shown below
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer carry or timer capture
A non-maskable software error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources This bit is reset
when interrupt is acknowledged
ENI and ENTI bits select external and timer interrupts re-
spectively Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled
IEDG selects the external interrupt edge (0 e rising edge
1 e falling edge) The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt
IPND and TPND bits signal which interrupt is pending After
an interrupt is acknowledged the user can check these two
bits to determine which interrupt is pending This permits the
interrupts to be prioritized under software The pending flags
have to be cleared by the user Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts
The software interrupt does not reset the GIE bit This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt
INTERRUPT PROCESSING
The interrupt once acknowledged pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts The microcontroller then
vectors to the address 00FFH and resumes execution from
that address This process takes 7 cycles to complete At
the end of the interrupt subroutine any of the following
three instructions return the processor back to the main pro-
gram RET RETSK or RETI Either one of the three instruc-
tions will pop the stack into the program counter (PC) The
stack pointer is then incremented twice The RETI instruc-
tion additionally sets the GIE bit to re-enable further inter-
rupts
Any of the three instructions can be used to return from a
hardware interrupt subroutine The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop
Note There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit the interrupt enable bit will be reset
but an interrupt may still occur This is because interrupt processing is
started at the same time as the interrupt bit is being reset To avoid
this scenario the user should always use a two three or four cycle
instruction to reset interrupt enable bits
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors noise and ‘‘brown out’’ voltage drop situations Spe-
cifically it detects cases of executing out of undefined ROM
area and unbalanced tack situations
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents The opcode for a software interrupt is
also ‘‘00’’ Thus a program accessing undefined ROM will
cause a software interrupt
Reading an undefined RAM location returns an FF (hexade-
cimal) The subroutine stack on the device grows down for
each subroutine call By initializing the stack pointer to the
top of RAM the first unbalanced return instruction will cause
the stack pointer to address undefined RAM As a result the
program will attempt to execute from FFFF (hexadecimal)
which is an undefined ROM location and will trigger a soft-
ware interrupt
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FIGURE 17 Interrupt Block Diagram
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