LM3481 Datasheet, PDF (11/22 Pages) National Semiconductor (TI) – High Efficiency Low-Side N-Channel Controller for Switching Regulators

It is good design practice to only add as much slope com-
pensation as needed to avoid subharmonic oscillation. Addi-
tional slope compensation minimizes the influence of the
sensed current in the control loop. With very large slope com-
pensation the control loop characteristics are similar to a
voltage mode regulator which compares the error voltage to
a saw tooth waveform rather than the inductor current.
FREQUENCY ADJUST/SYNCHRONIZATION/SHUTDOWN
The switching frequency of the LM3481 can be adjusted be-
tween 100 kHz and 1 MHz using a single external resistor.
This resistor must be connected between the FA/SYNC/SD
pin and ground, as shown in Figure 7. Please refer to the typ-
ical performance characteristics to determine the value of the
resistor required for a desired switching frequency.
The following equation can also be used to estimate the fre-
quency adjust resistor.
Where f_S is in kHz and R_FA in kΩ.
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FIGURE 5. Increasing the Slope of the Compensation
Ramp
The LM3481 can be synchronized to an external clock. The
external clock must be connected between the FA/SYNC/SD
pin and ground, as shown in Figure 8. The frequency adjust
resistor may remain connected while synchronizing a signal,
therefore if there is a loss of signal, the switching frequency
will be set by the frequency adjust resistor.
It is also necessary to have the width of the synchronization
pulse narrower than the duty cycle of the converter and to
have the synchronization pulse width ≥ 300 ns.
The FA/SYNC/SD pin also functions as a shutdown pin. If a
high signal (refer to the electrical characteristics section for
definition of high signal) appears on the FA/SYNC/SD pin, the
LM3481 stops switching and goes into a low current mode.
The total supply current of the IC reduces to 5 µA, typically,
under these conditions.
Figure 9 and Figure 10 shows an implementation of a shut-
down function when operating in frequency adjust mode and
synchronization mode respectively. In frequency adjust
mode, connecting the FA/SYNC/SD pin to ground forces the
clock to run at a certain frequency. Pulling this pin high shuts
down the IC. In frequency adjust or synchronization mode, a
high signal for more than 30 µs shuts down the IC.
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FIGURE 6. ΔV_SL vs R_SL
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