SM5166AV Datasheet, PDF (9/11 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5166AV
Boost-up Signal
If the PLL momentarily loses lock as a result of a
phase error, a level signal is output on pin DB. When
the PLL is operating in lock, output DB goes high
impedance.
When the PLL starts up, the signal on DB charges
the low-pass filter capacitor in anticipation of high-
speed locking. After the boost-up signal is output and
the PLL phase error comes within tolerance, the
boost-up circuit stops and operation continues when
the 2 supplies (V_DD1, V_DD2) are applied and OPR
goes HIGH once only. After the boost-up circuit
stops, new data is written and the boost-up signal is
not output even if the VCO is not in lock.
Operating principles
When the PLL is operating with a phase error within
fixed tolerance, an internal WINDOWN signal is
generated, as shown in figure 6. This signal is in sync
with the N counter output signal (FV) and is 64
cycles of the FIN input period in length centered
about the falling edge of FV.
If the phase detector error correction signal occurs
before the WINDOWN LOW-level pulsewidth, the
HIGH-level output from DB continues. However, if
the error correction signal occurs wholly within the
WINDOWN LOW-level pulsewidth, DB goes high
impedance and the boost-up circuit operation stops.
The above description applies when the error
correction signal is revising up. When the error
correction signal is revising down, DB goes LOW.
FR
FV
Phase Detector
error correction signal
WINDOWN
∗∗
∗^{( : 32fFIN )}
∗∗
DB
Hi-Impedance
HIGH level output
Hi-Impedance
Figure 6. boost-up signal timing
Standby Mode
current consumption and reduce power dissipation.
The SM5166AV enters standby mode when OPR
goes LOW. In this mode, the states and functions
shown in table 2 occur.
In standby mode, some current flows into VDD1
(FIN and XIN prescaler current). Therefore, it is
necessary to reduce V_DD1 to 0 V to fully reduce
Table 2. Standby mode block states
Block
DO and DB
LD
Phase
comparator
State
Floating (high impedance)
LOW-level output
Reset
Input FIN
Feedback resistor is cutoff (HIGH level)
Input XIN
Feedback resistor is cutoff (HIGH level)
N counter
Reset
R counter
Reset
Latch data
Stored (while V_DD2 is within rating)
NIPPON PRECISION CIRCUITS—9