SM5166AV Datasheet, PDF (6/11 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

Input Data Format
Shift register timing
SM5166AV
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
DATA MSB
LSB
CONTROL
LE
Figure 1. Comparator data format
Latch select
The last (17th) data bit determines the status of the
shift register data latch.
Table 1. Latch select bit function
Bit 17
0
1
Latch
Swallow counter and main counter frequency divider
ratio latch select
Reference frequency counter divider ratio data and
LD output latch select
Swallow counter and main counter frequency divider
MSB
LSB
DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
2¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
Main counter
Swallow counter
(11-bit : 32 to 2047)
(5-bit : 0 to 31)
Latch selection bit : Set to "0"
Figure 2. Swallow counter and main counter frequency divider data format
Input data example
If the VCO output (f_VCO) is trebled, the output
frequency (f_LO) is 251.3 MHz, and the channel
bandwidth (f_CH: operating frequency (f_R) × 3) is 25
kHz, then the comparator frequency divider ratio N
is given by:
N = _f-f--CL----^OH-- = ^f---V--f--_RC----^O-_×-----^×_3----3-- = ^{20---5.--0-1--2-.--35----⁄⁄}---33- = 10052 = 32 × 314 + 4
Therefore, the swallow counter count is 4 (00100)₂
and the main frequency divider counter count is 314
(0000100111010)₂. The input data format is shown
in figure 3.
NIPPON PRECISION CIRCUITS—6