SM5166AV Datasheet, PDF (7/11 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5166AV
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Input
Data
2¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
00100111010001000
Main counter
Swallow counter
(11-bit : 32 to 2047)
(5-bit : 0 to 31)
Latch selection bit : Set to "0"
Figure 3. Swallow counter and main counter frequency divider data example
Reference counter frequency divider setting
MSB
LSB
DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
2¹² 2¹¹ 2¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
(Reference counter 13-bit : 5 to 8191)
LD output setting bit^∗
Test bits : (15, 16) = (0, 0) for normal operation
Latch selection bit : Set to "1"
∗ ^{: Normal operation when 1,}
LOW-level output when 0.
Figure 4. Reference counter data and LD output setting format
Input data example
If the VCO output (f_VCO) is trebled, the crystal
frequency is 12.8 MHz and the channel bandwidth
(f_CH: comparator frequency (f_R) × 3) is 25 kHz, then
the reference frequency divider ratio R is given by:
NR
=
X-----t--a---l
f_CH
=
-f--X_R----t-_×-a---l-3-
=
0---.--01---22---5.--8--⁄^---3-
=
1536
=
8 × 192
Therefore, the reference counter count is 192
(00011000000)₂. The input data format is shown in
figure 5.
NIPPON PRECISION CIRCUITS—7