SM5859AF Datasheet, PDF (3/33 Pages) Nippon Precision Circuits Inc – compression and non compression type antishock memory controller

Pin description
SM5859AF
Pin number
Pine name
1
VDD
2
UC1
3
UC2
4
UC3
5
UC4
6
UC5
7
NTEST1
8
NTEST2
9
CLK
10
VSS
11
YSRDATA
12
YLRCK
13
YSCK
14
ZSCK
15
ZLRCK
16
ZSRDATA
17
YFLAG
18
YFCLK
19
YBLKCK
20
NRESET
21
ZSENSE
22
UC6
23
YDMUTE
24
YMLD
25
YMDATA
26
YMCLK
27
NOE
(NCAS2)
28
NCAS
29
D2
30
D3
31
D0
32
D1
33
NWE
34
NRAS
35
A9
36
A8
37
A7
38
A6
39
A5
40
A4
41
A0
42
A1
43
A2
44
A3
Ip : Input pin with pull-up resistor
I/O
-
Ip/O
Ip/O
Ip/O
Ip/O
Ip/O
Ip
Ip
I
-
I
I
I
O
O
O
I
I
I
I
O
Ip/O
I
I
I
I
O
O
O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
Function
VDD supply pin
Microcontroller interface extension I/O 1
Microcontroller interface extension I/O 2
Microcontroller interface extension I/O 3
Microcontroller interface extension I/O 4
Microcontroller interface extension I/O 5
Test pin
Test pin
16.9344 MHz clock input
Ground
Audio serial input data
Audio serial input LR clock
Audio serial input bit clock
Audio serial output bit clock
Audio serial output LR clock
Audio serial output data
Signal processor IC RAM overflow flag
Crystal-controlled frame clock
Subcode block clock signal
System reset pin
Microcontroller interface status output
Microcontroller interface extension I/O 6
Forced mute pin
Microcontroller interface latch clock
Microcontroller interface serial data
Microcontroller interface shift clock
DRAM OE control (with single DRAM)
DRAM2 CAS control (with 2 DRAMs)
DRAM CAS control
DRAM data input/output 2
DRAM data input/output 3
DRAM data input/output 0
DRAM data input/output 1
DRAM WE control
DRAM RAS control
DRAM address 9
DRAM address 8
DRAM address 7
DRAM address 6
DRAM address 5
DRAM address 4
DRAM address 0
DRAM address 1
DRAM address 2
DRAM address 3
Setting
H
L
Test
Test
Left channel Right channel
Left channel Right channel
Overflow
Reset
Mute
Ip/O : Input/Output pin (With pull-up resistor when a input mode)
NIPPON PRECISION CIRCUITS-3