SM5859AF Datasheet, PDF (27/33 Pages) Nippon Precision Circuits Inc – compression and non compression type antishock memory controller

SM5859AF
Through-mode operation
If MSON is set LOW (80H command), an operating
mode that does not perform shock-proof functions
becomes active. In this case, input data is passed
as-is (after attenuator and mute operations) to the
output. External DRAM is not accessed.
- In this case, input data needs to be at a rate fs
and the input word clock must be synchronized to
the CLK input (384fs). However, short range jitter
can be tolerated (jitter-free system).
LOW. Accordingly, to provide for the largest possi-
ble jitter margin, it is necessary that the YLRCK
clock be at rate fs by the time jitter-free timing
starts.
The jitter margin is 0.2/ fs.
This jitter margin is the allowable difference
between the system clock (CLK) 1/ 384 divided, fs
rate clock and the YLRCK input clock.
- Jitter-free system timing starts from the first
YLRCK rising edge after either (A) a reset
(NESET= 0) release by taking the reset input from
LOW to HIGH or (B) by taking MSON from HIGH to
If the timing difference exceeds the jitter margin,
irregular operation like data being output twice or
conversely complete “1” data output may occur. In
the worst case, a click noise will also be generated.
Attenuation
- The attenuation register is set by the 84H com-
mand.
- The attenuation register set value becomes active
when the 83H command sets the ATT flag to 1.
When the ATT flag is 0, the attenuation register
value is considered to be the equivalent of 256 for a
maximum gain of 0 dB.
- The gain (dB) is given from the set value (Datt)
by the following equation.
Gain = 20 × log(Datt/256) [dB]; left and right chan-
nels
- For the maximum attenuation register set value
(Datt = 255), the corresponding gain is -0.03 dB.
But when the ATT flag is 0 (Datt = 256), there is no
attenuation.
- After a system reset initialization, the attenuation
register is set to 64 (-12 dB). However, because the
ATT flag is reset to 0, there is no attenuation.
- When the attenuation register setting changes or
when the ATT flag changes, the gain changes
smoothly from the previous set gain towards the
new set value. If a new value for the attenuation
level is set before the previously set level is
reached, the gain changes smoothly towards the
latest setting.
The gain changes at a rate of 4 × (1/fs) per step. A
full-scale change (255 steps) takes approximately
23.3 ms (when fs = 44.1 kHz). See fig 3.
set 1
Gain
set 3
set 5
set 2
set 4
time
Fig 3 Attenuation operation example
NIPPON PRECISION CIRCUITS-27