SM5902AF Datasheet, PDF (25/40 Pages) Nippon Precision Circuits Inc – compression and non compression type shock-proof memory controller

SM5902AF
YFLAG, YFCLK, FLAG6
Correct data demodulation becomes impossible for
the CD signal processor IC when a disturbance
exceeding the RAM jitter margin occurs. The
YFLAG signal input pin is used to indicate when
such a condition has occurred.
The YFCLK is a 7.35 kHz clock synchronized to the
CD format frame 1.
The IC checks the YFLAG input and stops the
encode sequence when such a disturbance has
occurred, and then makes FLAG6 active.
The YFLAG check method used changes depend-
ing on the YFLGS flag and YFCKP flag (85H com-
mand). See table1.
If YFLAGS is set to 1, then YFCLK should be tied
either High or Low.
85H command
YFLGS YFCKP
FLAG6 set conditions
1
0
0
When YFLAG=LOW on YFCLK input falling edge
2
1
When YFLAG=LOW on YFCLK input rising edge
3
1
0
When YFLAG=LOW YFCLK be tied either High or Low
4
1 When YFLAG=HIGH
FLAG6 reset conditions
- By status read (90H command)
- When MSON=LOW
- After system reset
Table 1. YFLAG signal check method
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