SM5902AF Datasheet, PDF (24/40 Pages) Nippon Precision Circuits Inc – compression and non compression type shock-proof memory controller

RAM addresses
SM5902AF
The SM5902 uses either 1 or 2 external 1M or 4M
DRAMs as external buffers.
Three kinds of addresses are used for external
RAM control.
WA (write address)
RA (read address)
VWA (valid write address)
Among these, VWA is the write address for con-
forming data whose validity has been confirmed.
Determination of the correctness of data read from
the CD is delayed relative to the encode write pro-
cessing, so VWA is always delayed relative to WA.
The region available for valid data is the area
between VWA-RA.
- Connect data work area
This is an area of memory reserved for connect
data. This area is 2k bits if using 1M DRAMs, 4k
bits if using 4M DRAMs, or 8k bits if using 16M
DRAMs.
Connect data work area
RA
WA
VWA
Valid data
area
Fig 1. RAM addresses
VWA (valid write address)
The VWA is determined according to the YBLKCK
pin and WAQV command. Refer to the timing chart
below.
1.YBLKCK is a 75 Hz clock(HIGH for 136 µs) when
used for normal read mode and it is a 150 Hz clock
when used for double-speed read mode, synchro-
nized to the CD format block end timing.
When this clock goes LOW, WA which is the write
address of internal encode sequence, is stored
(see note 2).
2.The microcontroller checks the subcode and, if
confirmed to be correct, generates a WAQV com-
mand (80H).
3.When the WAQV command is received, the previ-
ously latched WA is stored as the VWA.
(note 2) Actually, there is a small time difference, or
gap, between the input data and YBLKCK. This gap
serves to preserves the preceding WA to protect
against incorrect operation.
YBLKCK
Microcontroller data set
Refer to Microcontroller interface
VWA
13.3ms
VWA latch set
WAQV set
VWA(x)
VWA(x + 1)
Values shown are for rate fs. The values are 1/2 those shown at rate 2fs.
Fig 2. YBLKCK and VWA relationship
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