SM5903CF Datasheet, PDF (24/31 Pages) Nippon Precision Circuits Inc – compression and non compression type anti-shock memory controller

SM5903CF
Encode sequence temporary stop
- When RAM becomes full, MSWREN is set LOW
using the 80H command and encode sequence
stops. (For details of the stop conditions, refer to
the description of the ENCOD flag.)
- Then, if MSWREN is set HIGH without issuing a
compare-connect start command, the encode
sequence re-starts. At this time, newly input data is
written not to VWA, but to WA. In this way, the data
already written to the region between VWA and WA
is not lost.
- But if the MSWREN is set HIGH (80H command)
after using the compare-connect start command
even only once, data is written to VWA. If data is
input before comparison and conformance is
detected, the same operation as direct-connect
mode takes place when the command is issued.
After comparison and conformance are detected,
no operation is performed because the encode
sequence has already been started. However,
make sure that the other bit settings within the
same 80H command are valid.
DRAM refresh
- DRAM initialization refresh
A 15-cycle RAS-only refresh is carried out for
DRAM initialization under the following condition.
When MSON changes from 0 to 1 in command
80H.
When from MSON=1, MSRDEN=0 and
MSWREN=0 states only MSWREN changes to 1.
In this case, encode sequence immediately starts
and initial data is written (at 2fs rate input) after a
delay of 0.7ms.
- Refresh during Shock-proof mode operation
In this IC, a data access operation to any address
also serves as a data refresh. Accordingly, there
are no specific refresh cycles other than the initial-
ization refresh cycle (described above).
This has the resulting effect of saving on DRAM
power dissipation.
A data access to DRAM can occur in an encode
sequence write operation or in a decode sequence
read operation. In an encode sequence write oper-
ation the connect operation is stopped, while in a
decode sequence read operation the data is always
output to the D/A converter in a fixed manner. The
refresh rate for each DRAM during decode
sequence is shown in the table below.
The decode sequence, set by MSON=1 and MSR-
DEN=1, operates when valid data is in DRAM
(when MSEMP=0).
- When MSON=0, DRAM is not refreshed because
no data is being accessed.Although MSON=1,
DRAM is not refreshed if ENCOD=0 and DECOD=0
(both encode and decode sequence are stopped).
Data compression mode
4 bit
5 bit
6 bit
Full bit
1M (256K×4 bits)
5.44 ms
4.35 ms
3.63 ms
1.36 ms
DRAMs used (same for 1 or 2 DRAMs)
4M (1M×4 bits)
10.88 ms
8.71 ms
7.26 ms
2.72 ms
16M(4M×4 bits)
21.77ms
17.42ms
14.52ms
5.81ms
Table 2. Decode sequence refresh rate
NIPPON PRECISION CIRCUITS-24