UPD98402A Datasheet, PDF (9/26 Pages) NEC – LOCAL ATM SONET FRAMER

µPD98402A
• Power supply
Symbol
VDD
GND
Pin No.
I/O
1, 20, 33, 40, –
52, 55, 57, 60,
81, 100, 120,
137, 150
Supply voltage, 5 V ±5 %
21, 34, 41, 42, –
47, 51, 56, 61,
64, 68, 72, 79,
80, 94, 101,
107, 113, 121,
122, 128, 138,
140, 147, 149,
159, 160
Ground
Function
• ATM Layer Interface
Symbol
Pin No.
I/O
RDO0-RDO7
151-158
O
RCLK
RSOC
148
I
145
O
RENBL
EMPTY
146
I
144
O
TDI0-TDI7
129-136
I
TCLK
TSOC
139
I
142
I
TENBL
FULL
141
I
143
O
I/O Level
CMOS
TTL
CMOS
TTL
CMOS
TTL
TTL
TTL
TTL
CMOS
Function
Connected to 8-bit data bus to output the receive data to the
ATM Layer device. Output is synchronized with the RCLK
rising up. To be undefined after reset.
Input pin of the receive data transferring clock from the ATM
Layer device.
Receive cell start address signal. To the ATM Layer device,
this signal indicates the start address byte of the receive ATM
cell. To be undefined after reset.
Receive enable signal. Input pin of the signal indicating that
the ATM layer device can receive data.
Output buffer empty signal. This signal indicates that there is
no data to be transferred to the receive FIFO of the
µPD98402A. To be inactive after reset.
8-bit data bus to input the transmit data from the ATM Layer
device. Reading a data on the bus is synchronized with the
TCLK rising-up.
Input pin of the transmit data transferring clock from the ATM
layer device.
Transmit cell start address signal. Input pin of the signal
indicating the start byte of the transmit ATM cell input from the
ATM Layer device to the µPD98402A.
Transmit enable signal. This signal indicates that the ATM
Layer device is transmitting the valid data to the TDI0-TDI7.
Input buffer full signal. When 4 bytes remain as the
acceptable bytes of transmit FIFO at last, this signal changes
to active. To be inactive after reset.
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