UPD98402A Datasheet, PDF (10/26 Pages) NEC – LOCAL ATM SONET FRAMER

µPD98402A
• Management Interface
Symbol
D0-D7
A0-A5
Pin No.
I/O
104-106
I/O
108-112
114-119
I
R/W
123
I
CE
ACK
PHINT
126
I
124
O
127
O
OE
125
I
• OAM Interface
Symbol
LOS
Pin No.
I/O
9
O
OOF
RAL
TAL
10
O
7
I
8
I
I/O Level
CMOS
TTL
TTL
TTL
CMOS
CMOS
TTL
Function
8-bit data bus for data transfer between the control processor
and the internal register of the µPD98402A.
Address bus. Used for setting the internal register address of
the µPD98402A.
Read/write control signal.
Low level: Write cycle
High level: Read cycle
Chip enable signal.
At low level, internal register access is to be enable.
Read/write cycle receive acknowledge or ready signal.
After reset, this signal indicates inactive level.
Signal which indicates the interrupt cause occurrence to the
processor.
After reset, this signal indicates inactive level.
Output enable. When this signal is set to low level, the
µPD98402A outputs data to the control bus. Even if the CE
signal is inactive, when this signal is at low level, the
µPD98402A drives the control bus.
I/O Level
CMOS
CMOS
TTL
TTL
Function
Loss of signal detection. Output high level when receive serial
data input is "0" for 50 µs continuously or optical input stop
signal (RAL) is input. When 2 consecutive frames of valid
synchronous pattern is detected, or when input of the optical
input stop signal is released, low level is output. To be
inactive after reset.
Out of frame detection. When 4 consecutive frames of wrong
synchronous pattern are detected, high level is output. When
2 consecutive frames of normal synchronous pattern are
detected, low level is output. To be inactive after reset.
Receive alarm. Inputs receiver-side optical input stop signal
by the optical module.
Low level: Normal
High level: Optical input stopped.
Transmit alarm. Inputs transmit-side optical output stop signal
output by the optical module.
Low level: Normal
High level: Optical output stopped.
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