UPD98402A Datasheet, PDF (15/26 Pages) NEC – LOCAL ATM SONET FRAMER

µPD98402A
AC Characteristics
(1) Management Interface
Internal Register Read/Write
Parameters
A0-A5 setup time (to CE↓)
R/W setup time (to CE↓)
A0-A5 hold time (to CE↓)
R/W hold time (to CE↓)
CE↓→ACK↓ delay time (read)
CE↓→ACK↓ delay time (write)
CE↑→ACK↑ delay time
CE↓→ data output delay time
OE↓→ data output delay time
OE↑→ data floating output delay time
D0-D7 setup time (to CE↓)
D0-D7 hold time (to CE↓)
CE low-level width
Symbol
Conditions
tSCC1
tSCC2
tHCC1
tHCC2
tDCNAR
Load capacitor 15 pF
At parallel data input
Load capacitor 15 pF
At serial data input
tDCNAW Load capacitor 15 pF
At parallel data input
Load capacitor 15 pF
At serial data input
tDCPA
Load capacitor 15 pF
At parallel data input
Load capacitor 15 pF
At serial data input
tDCD Load capacitor 15 pF
At parallel data input
Load capacitor 15 pF
At serial data input
tDOD Load capacitor 15 pF
tFOD Load capacitor 15 pF
tSDC
tHCD
tCEBW At parallel data input
At serial data input
OE low-level width
tOEBW At parallel data input
At serial data input
MIN.
5
5
3
3
3×
tCYPPR
3×
(tCYPSR × 8)
2×
tCYPPR
2×
(tCYPSR × 8)
1×
tCYPPR
1×
(tCYPSR × 8)
2×
tCYPPR
2×
(tCYPSR × 8)
—
—
5
3
3.5 ×
tCYPPR
3.5 ×
(tCYPSR × 8)
2.5 ×
tCYPPR
2.5 ×
(tCYPSR × 8)
TYP.
MAX.
4.5 ×
tCYPPR
4.5 ×
(tCYPSR × 8)
3.5 ×
tCYPPR
3.5 ×
(tCYPSR × 8)
2.5 ×
tCYPPR
2.5 ×
(tCYPSR × 8)
3.5 ×
tCYPPR
3.5 ×
(tCYPSR × 8)
9.4
10
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks 1. For tCYPPR, refer to (6) PMD parallel interface timing.
2. For tCYPSR, refer to (7) PMD serial interface timing.
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