UPD784224 Datasheet, PDF (73/92 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784224, 784225, 784224Y, 784225Y
(d) I²C bus mode (µPD784225Y only)
Parameter
Symbol
SCL0 clock frequency
Bus free time (between stop
and start conditions)
Hold time^Note1
Low-level width of SCL0
clock
High-level width of SCL0
clock
Setup time of start/restart
conditions
Data hold When using
time
CBUS-compatible
master
When using I²C
bus
Data setup time
Rising time of SDA0 and
SCL0 signals
Falling time of SDA0 and
SCL0 signals
Setup time of stop condition
Pulse width of spike
restricted by input filter
Load capacitance of each
bus line
fCLK
tBUF
tHD : STA
tLOW
tHIGH
tSU : STA
tHD : DAT
tSU : DAT
tR
tF
tSU : STO
tSP
Cb
Standard Mode
MIN.
MAX.
0
100
4.7
−
4.0
−
4.7
−
4.0
−
4.7
−
5.0
−
0^{Note 2}
250
−
−
4.0
−
−
−
−
1,000
300
−
−
400
High-Speed Mode
Unit
MIN.
MAX.
0
400
kHz
1.3
−
µs
0.6
−
µs
1.3
−
µs
0.6
−
µs
0.6
−
µs
−
−
µs
0^{Note 2}
0.9^{Note 3}
µs
100^{Note 4}
−
ns
20 + 0.1Cb^{Note 5}
300
ns
20 + 0.1Cb^{Note 5}
300
ns
0.6
−
µs
0
50
ns
−
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time.
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on VIHmin.) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold
time tHD : DAT needs to be satisfied.
4. The high-speed mode I²C bus can be used in a standard mode I²C bus system. In this case, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low-level hold time
tSU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : DAT =
1,000 + 250 = 1,250 ns by standard mode I²C bus specification)
5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U12376EJ1V0DS00
73