UPD703130 Datasheet, PDF (55/72 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
IORD high-level width
Delay time from address to IORD ↑
Delay time from IORD ↑ to address
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
Symbol
<24>
<25>
<32>
<33>
tSWK
tHKW
tWRDL
tWRDH
<34>
<35>
<56>
<57>
<58>
tDARD
tDRDA
tASR
tRAH
tASC
<59>
tCAH
<60>
tRC
Condition
RAS precharge time
<61>
RAS hold time
<63>
Column address read time for RAS
<64>
CAS pulse width
<65>
CAS-RAS precharge time
<66>
CAS hold time
<67>
CAS precharge time
<71>
Delay time from RAS to column address <76>
RAS-CAS delay time
<77>
CAS precharge time
<81>
High-speed page mode cycle time
<82>
RAS hold time for CAS precharge
<83>
WE hold time (from CAS ↓)
<85>
WE read time (from RAS ↑)
<88>
tRP
tRSH
tRAL
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tCP
tPC
tRHCP
tWCH
tRWL
wCP = 0
MIN.
15
2
(2 + wRH + wDA + wF + w)T – 10
T – 10
0.5T – 10
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
(1.5 + wDA + wF)T – 10
(3 + wRP + wRH + wDA + wF + w)T
– 10
(0.5 + wRP)T – 10
(1.5 + wDA + wF)T – 10
(2 + wCP + wDA + wF + w)T – 10
(1 + wDA + wF)T – 10
(1 + wRP)T – 10
(2 + wRH + wDA + wF + w)T – 10
(2 + wRP + wRH + w)T – 10
(0.5 + wRH)T – 10
(1 + wRH + w)T – 10
(0.5 + wCP + w)T – 10
(2 + wCP + wDA + wF + w)T – 10
(2.5 + wCP + wDA + w)T – 10
(1 + wDA)T – 10
(1.5 + wDA + w)T – 10
MAX. Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: The number of idle states that are inserted when a write cycle follows a read cycle.
Preliminary Data Sheet U15390EJ1V0DS
55