UPD703130 Datasheet, PDF (48/72 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD703130
(e) Read timing (EDO DRAM) (3/3)
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
WE (Output)
OE (Output)
D0 to D15 (I/O)
BCYST (Output)
TRPW T1 TRHW T2 TDAW TCPW TB TDAW TE
<56>
<58>
<57>
<59>
Row address
Column address
<61>
<76>
Column address
<64>
<74>
<94>
<66>
<67>
<77>
<95>
<81>
<83>
<75>
<68>
<93>
<95>
<80>
<69>
<70>
<96>
Note
<97>
<100> <26> <37>
<75>
<74> <26>
<98>
<27>
<73>
<99>
Data
<27>
<78>
Data
WAIT (Input)
Note For on-page access from another cycle during the RASn low-level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
48
Preliminary Data Sheet U15390EJ1V0DS