UPD703130 Datasheet, PDF (42/72 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + w)T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + w)T
ns
– 10
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS pulse time
<62>
tRAS
(2.5 + wRH + wDA + w)T
ns
– 10
RAS hold time
<63>
tRSH
(1.5 + wDA + w)T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wDA + w)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + w)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRH)T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + w)T
ns
– 10
CAS precharge time
<71>
tCPN
(2 + wRP + wRH)T – 10
ns
RAS column address delay time
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
WE setup time (to CAS ↓)
<84>
tWCS
(1 + wRP + wRH )T
ns
– 10
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA + w)T – 10
ns
Data setup time (to CAS ↓)
<86>
tDS
(1.5 + wRP + wRH)T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(1.5 + wDA + w)T – 10
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
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Preliminary Data Sheet U15390EJ1V0DS