UPD703130 Datasheet, PDF (31/72 Pages) NEC – MOS INTEGRATED CIRCUIT

(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
CLKOUT (Output)
T1
TW
T2
µPD703130
A0 to A23 (Output)
CSn (Output)
RD (Output)
UWR, LWR (Output)
<33>
<34>
<32>
<35>
<48>
DMAAKm (Output)
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
<49>
<41>
<44>
<42>
<45>
<50>
<43>
<37>
<38>
<24>
<25>
<24>
<25>
<39>
<40>
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
31