UPD78P4916 Datasheet, PDF (32/56 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD78P4916
Other Operations (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Timer unit input low level width
Timer unit input high level width
Timer unit input signal valid edge
input cycle
CSYNCIN low level width
CSYNCIN high level width
Digital noise
eliminator
Eliminated pulse
width
Passed pulse width
NMI low level width
NMI high level width
INTP0 and INTP3 low level width
INTP0 and INTP3 high level width
INTP1, KEY0 - KEY4 low level
width
INTP1, KEY0 - KEY4 high level
width
INTP2 low level width
INTP2 high level width
RESET low level width
Symbol
tWCTL
tWCTH
tPERIN
tWCR1L
tWCR1H
tWSEP
tWNIL
tWNIH
tWIPL0
tWIPH0
tWIPL1
tWIPH1
tWIPL2
tWIPH2
tWRSL
Conditions
at DFGIN, CFGIN, DPGIN, REEL0IN,
REEL1IN logic level input
at DFGIN, CFGIN, DPGIN, REEL0IN,
REEL1IN logic level input
DFGIN, CFGIN and DPGIN input
MIN.
tCLK1
MAX.
Unit
ns
tCLK1
ns
2
µs
Digital noise eliminator not used
8tCLK1
ns
Digital noise eliminator used
(INTM2 bit 4 = 0)
108tCLK1
ns
Digital noise eliminator used
(INTM2 bit 4 = 1)
180tCLK1
ns
Digital noise eliminator not used
8tCLK1
ns
Digital noise eliminator used
(INTM2 bit 4 = 0)
108tCLK1
ns
Digital noise eliminator used
(INTM2 bit 4 = 1)
180tCLK1
ns
INTM2 bit 4 = 0
104tCLK1 ns
INTM2 bit 4 = 1
176tCLK1 ns
INTM2 bit 4 = 0
108tCLK1
ns
INTM2 bit 4 = 1
180tCLK1
ns
VDD = AVDD = 2.7 to 5.5 V
10
µs
VDD = AVDD = 2.7 to 5.5 V
10
µs
2tCLK1
ns
2tCLK1
ns
Other than in STOP mode
2tCLK1
ns
When cancelling STOP mode
10
µs
Other than in STOP mode
2tCLK1
ns
When cancelling STOP mode
10
µs
Main clock operation Sampled at fCLK
2tCLK1
ns
in normal mode
Sampled at fCLK/128 32 ^Note
µs
Subclock operation Sampled at fCLK
61
µs
in normal mode
Sampled at fCLK/128 7.9 ^Note
ms
When cancelling STOP mode
10
µs
Main clock operation Sampled at fCLK
2tCLK1
ns
in normal mode
Sampled at fCLK/128 32 ^Note
µs
Subclock operation Sampled at fCLK
61
µs
in normal mode
Sampled at fCLK/128 7.9 ^Note
ms
When cancelling STOP mode
10
µs
10
µs
Note If a high level or low level is input two times in succession during the sampling period, high level or low
level is detected.
Remark tCLK1: Operation clock cycle time for peripheral unit (125 ns).
32