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UPD78P4916 Datasheet, PDF (31/56 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER | |||
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µPD78P4916
AC Characteristics
CPU and peripheral unit operation clocks (TA = â10 to +70 ËC, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
TYP. Unit
CPU operation clock cycle time
tCLK
fXX = 16 MHz VDD = AVDD = 4.0 to 5.5 V
CPU function only
125
ns
fXX = 16 MHz
fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1)
Peripheral unit operation clock
cycle time
tCLK1
fXX = 16 MHz
125
ns
fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1)
Serial interface
(1) SIOn: n = 1, 2 (TA = â10 to +70 ËC, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Serial clock cycle time
Serial clock high/low level width
SIn set-up time (to SCKn â)
SIn hold time (from SCKn â)
SOn output delay time (from SCKn â)
Symbol
tCYSK
tWSKH
tWSKL
tSSSK
tHSSK
tDSSK
Input
Output
Input
Output
Conditions
External clock
fCLK1/8
fCLK1/16
fCLK1/32
fCLK1/64
fCLK1/128
fCLK1/256
External clock
Internal clock
MIN. MAX. Unit
1.0
µs
1.0
µs
2.0
µs
4.0
µs
8.0
µs
16
µs
32
µs
420
ns
tCYSK/2â50
ns
100
ns
400
ns
0
300
ns
Remarks 1. fCLK1: Operation clock for peripheral unit (8 MHz)
2. n = 1, 2
(2) Only SIO2 (TA= â10 to +70 ËC, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
SCK2(8) â â STRB â
Strobe high level width
BUSY setup time (to BUSY detection timing)
BUSY hold time (from BUSY detection timing)
Busy inactive â SCK2(1) â
Symbol
tDSTRB
tWSTRB
tSBUSY
tHBUSY
tLBUSY
Conditions
MIN. MAX.
tWSKH
tCYSK
tCYSKâ30 tCYSK+30
100
100
tCYSK+tWSKH
Unit
ns
ns
ns
Remarks 1. The value in the parentheses following SCK2 indicates the sequential number of the SCK2.
2. BUSY detection timing is (n + 2) Ã tCYSK (n = 0, 1,...) after SCK2(8) â.
3. BUSY inactive â SCK2(1) â is a value at the time data is already written in SIO2.
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