MC74HC4046A Datasheet, PDF (9/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
The XOR is more susceptible to locking onto harmonics of
the SIGIN than the digital phase detector 2. For instance, a
signal 2 times the VCO frequency results in the same output
duty cycle as a signal equal to the VCO frequency. The differ-
ence is that the output frequency of the 2f example is twice
that of the other example. The loop filter and VCO range
should be designed to prevent locking on to harmonics.
Phase Comparator 2
This detector is a digital memory network. It consists of
four flip–flops and some gating logic, a three state output and
a phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is in-
dependent of duty cycle.
Phase comparator 2 operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO out-
put and the signal input positive waveform edges. Figure 8
shows some typical loop waveforms. First assume that SIGIN
is leading the COMPIN. This means that the VCO’s frequen-
cy must be increased to bring its leading edge into proper
phase alignment. Thus the phase detector 2 output is set
high. This will cause the loop filter to charge up the VCO in-
put, increasing the VCO frequency. Once the leading edge of
the COMPIN is detected, the output goes TRI–STATE hold-
ing the VCO input at the loop filter voltage. If the VCO still
lags the SIGIN then the phase detector will again charge up
the VCO input for the time between the leading edges of both
waveforms.
If the VCO leads the SIGIN then when the leading edge of
the VCO is seen; the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
the SIGIN is detected at which time the output disables itself
again. This has the effect of slowing down the VCO to again
make the rising edges of both waveforms coincidental.
When the PLL is out of lock, the VCO will be running either
slower or faster than the SIGIN. If it is running slower the
phase detector will see more SIGIN rising edges and so the
output of the phase comparator will be high a majority of the
time, raising the VCO’s frequency. Conversely, if the VCO is
running faster than the SIGIN, the output of the detector will
be low most of the time and the VCO’s output frequency will
be decreased.
As one can see, when the PLL is locked, the output of
phase comparator 2 will be disabled except for minor correc-
tions at the leading edge of the waveforms. When PC2 is
TRI–STATED, the PCP output is high. This output can be
used to determine when the PLL is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase difference
between the COMPIN and the SIGIN. The lock range of the
PLL is the same as the capture range. Minimal power was
consumed in the loop filter since in lock the detector output is
a high impedance. When no SIGIN is present, the detector
will see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to fmin.
Phase comparator 2 is more susceptible to noise, causing
the PLL to unlock. If a noise pulse is seen on the SIGIN, the
comparator treats it as another positive edge of the SIGIN
and will cause the output to go high until the VCO leading
edge is seen, potentially for an entire SIGIN period. This
would cause the VCO to speed up during that time. When us-
ing PC1, the output of that phase detector would be disturbed
for only the short duration of the noise spike and would cause
less upset.
Phase Comparator 3
This is a positive edge–triggered sequential phase detec-
tor using an RS flip–flop as shown in Figure 6. When the PLL
is using this comparator, the loop is controlled by positive sig-
nal transitions and the duty factors of SIGIN and COMPIN
are not important. It has some similar characteristics to the
edge sensitive comparator. To see how this detector works,
assume input pulses are applied to the SIGIN and COMPIN’s
as shown in Figure 9. When the SIGIN leads the COMPIN,
the flop is set. This will charge the loop filter and cause the
VCO to speed up, bringing the comparator into phase with
the SIGIN. The phase angle between SIGIN and COMPIN va-
ries from 0° to 360° and is 180° at fo. The voltage swing for
PC3 is greater than for PC2 but consequently has more ripple
in the signal to the VCO. When no SIGIN is present the VCO
will be forced to fmax as opposed to fmin when PC2 is used.
The operating characteristics of all three phase compara-
tors should be compared to the requirements of the system
design and the appropriate one should be used.
SIGIN
COMPIN
PC2OUT
VCOIN
PCPOUT
VCC
GND
HIGH IMPEDANCE OFF–STATE
Figure 8. Typical Waveforms for PLL Using
Phase Comparator 2
SIGIN
COMPIN
PC3OUT
VCOIN
VCC
GND
Figure 9. Typical Waveform for PLL Using
Phase Comparator 3
High–Speed CMOS Logic Data
3–9
DL129 — Rev 6
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