MC74HC4046A Datasheet, PDF (7/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to op-
erate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 14). R2 can be used
to set the offset frequency with 0 volts at VCO input. For ex-
ample, if R2 is decreased, the offset frequency is increased.
If R2 is omitted the VCO range is from 0 Hz. The effect of R2
is shown in Figure 24, typical performance curves. By in-
creasing the value of R2 the lock range of the PLL is in-
creased and the gain (volts/Hz) is decreased. Thus, for a
narrow lock range, large swings on the VCO input will cause
less frequency variation.
Internally, the resistors set a current in a current mirror, as
shown in Figure 5. The mirrored current drives one side of
the capacitor. Once the voltage across the capacitor charges
up to Vref of the comparators, the oscillator logic flips the ca-
pacitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then tak-
en to VCO output (Pin 4).
The input to the VCO is a very high impedance CMOS in-
put and thus will not load down the loop filter, easing the fil-
ters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the VCO
input voltage is buffered through a unity gain Op–amp to De-
mod Output. This Op–amp can drive loads of 50K ohms or
more and provides no loading effects to the VCO input volt-
age (see Figure 12).
An inhibit input is provided to allow disabling of the VCO
and all Op–amps (see Figure 5). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Op–amps, minimizing standby power consump-
tion.
12
R2
VREF _{+_}
VCOIN 9
11
+_
R1
DEMODOUT ₁₀
+_
I1
CURRENT
MIRROR
I1 + I2 = I3
I2
I3
4 VCOOUT
C1
(EXTERNAL)
6
7
Vref
+
+
INH ₅
Figure 5. Logic Diagram for VCO
High–Speed CMOS Logic Data
3–7
DL129 — Rev 6
MOTOROLA