MC74HC4046A Datasheet, PDF (8/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
The output of the VCO is a standard high speed CMOS
output with an equivalent LS–TTL fan out of 10. The VCO
output is approximately a square wave. This output can ei-
ther directly feed the COMPIN of the phase comparators or
feed external prescalers (counters) to enable frequency syn-
thesis.
Phase Comparators
All three phase comparators have two inputs, SIGIN and
COMPIN. The SIGIN and COMPIN have a special DC bias
network that enables AC coupling of input signals. If the sig-
nals are not AC coupled, standard 54HC/74HC input levels
are required. Both input structures are shown in Figure 6.
The outputs of these comparators are essentially standard
54HC/74HC outputs (comparator 2 is TRI–STATEABLE). In
normal operation VCC and ground voltage levels are fed to
the loop filter. This differs from some phase detectors which
supply a current to the loop filter and should be considered in
the design. (The MC14046 also provides a voltage).
VCC
SIGIN
14
VCC
PC2OUT
13
VCC
COMPIN
3
PCPOUT
1
PC3OUT
15
PC1OUT
2
Figure 6. Logic Diagram for Phase Comparators
Phase Comparator 1
This comparator is a simple XOR gate similar to the
54/74HC86. Its operation is similar to an overdriven bal-
anced modulator. To maximize lock range the input frequen-
cies must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output volt-
age. The frequency range upon which the PLL will lock onto
if initially out of lock is defined as the capture range. The cap-
ture range for phase detector 1 is dependent on the loop filter
design. The capture range can be as large as the lock range,
which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference
between COMPIN and SIGIN will increase. At an input fre-
quency equal to fmin, the VCO input is at 0 V. This requires
the phase detector output to be grounded; hence, the two in-
put signals must be in phase. When the input frequency is
fmax, the VCO input must be VCC and the phase detector in-
puts must be 180 degrees out of phase.
SIGIN
COMPIN
PC1OUT
VCC
VCOIN
GND
Figure 7. Typical Waveforms for PLL Using
Phase Comparator 1
MOTOROLA
3–8
High–Speed CMOS Logic Data
DL129 — Rev 6