MC9S12A128 Datasheet, PDF (81/92 Pages) Motorola, Inc – Microcontroller unit (MCU)

MC9S12A128 Device Guide — V01.01
Table A-17 SPI Master Mode Timing Characteristics¹
Conditions are shown in Table A-4 unless otherwise noted, C_LOAD = 200pF on all outputs
Num C
Rating
Symbol Min
Typ
Max
Unit
1 P Operating Frequency
f_op
DC
—
1/4
f_bus
1 P SCK Period t_sck = 1./f_op
t_sck
4
—
2048
t_bus
2 D Enable Lead Time
t_lead
1/2
—
—
t_sck
3 D Enable Lag Time
t_lag
1/2
—
—
t_sck
4 D Clock (SCK) High or Low Time
t_wsck
t_bus − 30
—
1024 t_bus
ns
5 D Data Setup Time (Inputs)
t_su
25
—
—
ns
6 D Data Hold Time (Inputs)
t_hi
0
—
—
ns
9 D Data Valid (after Enable Edge)
t_v
—
—
25
ns
10 D Data Hold Time (Outputs)
t_ho
0
—
—
ns
11 D Rise Time Inputs and Outputs
t_r
—
—
25
ns
12 D Fall Time Inputs and Outputs
t_f
—
—
25
ns
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.
A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
1
12
2
4
4
11
11 3
12
8
7
9
10
10
MISO
(OUTPUT)
SLAVE MSB OUT
BIT 6 . . . 1
SLAVE LSB OUT
MOSI
(INPUT)
5
6
MSB IN
BIT 6 . . . 1
LSB IN
Figure A-7 SPI Slave Timing (CPHA = 0)
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