MC9S12A128 Datasheet, PDF (51/92 Pages) Motorola, Inc – Microcontroller unit (MCU)

MC9S12A128 Device Guide — V01.01
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for
information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT),
module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module
(BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number,
S12CRGV3/D) for information about the Clock and Reset Generator module.
7.1 Device-Specific Information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Refer to Figure 2-3. Pierce Oscillator Connections (XCLKS=1) of the HCS12 Clock and Reset Generator
(CRG) Block Guide (Motorola document order number, S12CRGV3/D).
Section 8 Enhanced Capture Timer (ECT) Block Description
Consult the HCS12 16-Bit, 8-Channel Enhanced Capture Timer (ECT) Block Guide (Motorola document
order number, S12ECT16B8CV1/D) for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12A128.
Consult the HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola
document order number, S12ATD10B8CV2/D) for information about each Analog to Digital Converter
module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the HCS12 Inter-Integrated Circuit (IIC) Block Guide (Motorola document order number,
S12IICV2/D) for information about the Inter-IC Bus module.
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