MC9S12A128 Datasheet, PDF (26/92 Pages) Motorola, Inc – Microcontroller unit (MCU)

MC9S12A128 Device Guide — V01.01
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function 1
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
BKGD
Pin Name
Function 2
—
—
—
—
—
—
TAGHI
PAD15
AN15
PAD[14:8] AN[14:08]
PAD07
AN07
PAD[06:00]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
AN[06:00]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
Pin Name
Function 3
—
—
—
—
—
—
MODC
ETRIG1
—
ETRIG0
—
—
—
XCLKS
MODB
MODA
—
TAGLO
—
—
—
—
—
—
—
SS1
SCK1
MOSI1
MISO1
Pin Name
Function 4
—
—
—
—
—
—
—
—
—
—
—
—
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Description
V_DDPLL
V_DDR
N.A.
V_DDX
V_DDPLL
V_DDR
V_DDA
Oscillator Pins
External Reset
Test Input
Voltage Regulator Enable Input
PLL Loop Filter
Background Debug, Tag High, Mode Input
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of ATD1
Port AD Inputs, Analog Inputs AN[6:0]
of ATD1
Port AD Input, Analog Input AN7 of ATD0,
External Trigger Input of ATD0
Port AD Inputs, Analog Inputs AN[6:0] of
ATD0
Port A I/O, Multiplexed Address/Data
—
Port B I/O, Multiplexed Address/Data
—
Port E I/O, Access, Clock Select
—
Port E I/O, Pipe Status, Mode Input
—
Port E I/O, Pipe Status, Mode Input
—
Port E I/O, Bus Clock Output
—
Port E I/O, Byte Strobe, Tag Low
—
Port E I/O, R/W in expanded modes
—
V_DDR
Port E Input, Maskable Interrupt
—
Port E Input, Non Maskable Interrupt
—
Port H I/O, Interrupt
—
Port H I/O, Interrupt
—
Port H I/O, Interrupt
—
Port H I/O, Interrupt
—
Port H I/O, Interrupt, SS of SPI1
—
Port H I/O, Interrupt, SCK of SPI1
—
Port H I/O, Interrupt, MOSI of SPI1
—
Port H I/O, Interrupt, MISO of SPI1
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