MC9S12A128 Datasheet, PDF (74/92 Pages) Motorola, Inc – Microcontroller unit (MCU)

A.5 Reset, Oscillator and PLL
MC9S12A128 Device Guide — V01.01
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola
document order number, S12CRGV3/D) .
Table A-14 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
1 T POR release level
2 T POR assert level
3 D Reset input pulse width, minimum input time
4 D Startup from Reset
5 D Interrupt pulse width, IRQ edge-sensitive mode
6 D Wait recovery startup time
Symbol
V_PORR
V_PORA
PW_RSTL
n_RST
PW_IRQ
t_WRS
Min
—
0.97
2
192
20
—
Typ
—
—
—
—
—
—
Max
2.07
—
—
196
—
14
Unit
V
V
t_osc
n_osc
ns
t_cyc
A.5.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
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