MC9S12H256 Datasheet, PDF (80/130 Pages) Motorola, Inc – Device User Guide

MC9S12H256 Device User Gui^Fde^r—^eeV^s01^c.1^a8 ^{le Semiconductor, Inc.}
Table 5-1 Reset and Interrupt Vector Table
Vector Address
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
$FFB4, $FFB5
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
$FFAC, $FFAD
$FFAA, $FFAB
$FFA8, $FFA9
$FF98 to
$FFA7
$FF96, $FF97
$FF9E to
$FF95
$FF8C, $FF8D
$FF80 to
$FF8B
Interrupt Source
CRG PLL lock
CRG Self Clock Mode
Reserved
IIC Bus
EEPROM
FLASH
CAN0 wake-up
CAN0 errors
CAN0 receive
CAN0 transmit
CAN1 wake-up
CAN1 errors
CAN1 receive
CAN1 transmit
Motor Control Timer Overflow
PWM Emergency Shutdown
CCR
Mask
Local Enable
Reserved
I-Bit
CRGINT (LOCKIE)
I-Bit
CRGINT (SCMIE)
I-Bit
IBCR (IBIE)
Reserved
Reserved
I-Bit EECTL (CCIE, CBEIE)
I-Bit FCTL (CCIE, CBEIE)
I-Bit CAN0RIER (WUPIE)
I-Bit
CAN0RIER (CSCIE,
OVRIE)
I-Bit
CAN0RIER (RXFIE)
I-Bit CAN0TIER (TXEIE[2:0])
I-Bit CAN0RIER (WUPIE)
I-Bit
CAN1RIER (CSCIE,
OVRIE)
I-Bit
CAN1RIER (RXFIE)
I-Bit CAN1TIER (TXEIE[2:0])
Reserved
I-Bit
MCCTL1 (MCOCIE)
Reserved
I-Bit
PWMSDN(PWMIE)
Reserved
HPRIO Value
to Elevate
$C6
$C4
$C0
$BA
$B8
$B6
$B4
$B2
$B0
$AE
$AC
$AA
$A8
$96
$8C
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE: For devices assembled in 112-pin LQFP packages all non-bonded out pins should
be configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.
80
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