MC9S12H256 Datasheet, PDF (27/130 Pages) Motorola, Inc – Device User Guide

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$0000
$0400
$0800
$1000
$4000
$0000 1K Register Space
$03FF
$0000
$0FFF
$1000
$3FFF
$4000
Mappable to any 2K Boundary
4K Bytes EEPROM
initially overlapped by register space
Mappable to any 4K Boundary
12K Bytes RAM
Alignable to top ($1000 – $3FFF)
or bottom ($0000 – $2FFF)
Mappable to any 16K Boundary
0.5K, 1K, 2K or 4K Protected Sector
$8000
$C000
$FF00
$FFFF
VECTORS
NORMAL
SINGLE CHIP
16K Fixed Flash EEPROM
$7FFF
$8000 _{16K Page Window}
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000 _{16K Fixed Flash EEPROM}
VECTORS
EXPANDED*
VECTORS
SPECIAL
SINGLE CHIP
$FFFF
$FF00
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode
Figure 1-3 MC9S12H256 Memory Map
Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128.
Table 1-2 Device Memory Map MC9S12H128
Address
Module
$0000 – $0017
$0018 – $0019
$001A – $001B
$001C – $001F
$0020 – $0027
$0028 – $002F
$0030 – $0033
$0034 – $003F
$0040 – $006F
$0070 – $007F
$0080 – $00AF
$00B0 – $00BF
$00C0 – $00C7
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Device ID register (PARTID)
CORE (MEMSIZ, IRQ, HPRIO)
Reserved
CORE (Background Debug Mode)
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Standard Timer Module 16-bit 8 channels (TIM)
Reserved
Analog to Digital Converter 10-bit 16 channels (ATD)
Reserved
Inter Integrated Circuit (IIC)
Size
(Bytes)
24
2
2
4
8
8
4
12
48
16
48
16
8
27
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