MC9S12H256 Datasheet, PDF (115/130 Pages) Motorola, Inc – Device User Guide

A.6 SPI
Freescale Semicondu_Mc_Ct₉o_S1r₂,_HI₂n₅₆c_D._{evice User Guide — V01.18}
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
2
1
4
4
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
5
6
MSB IN²
BIT 6 . . . 1
MOSI
(OUTPUT)
9
MSB OUT²
9
BIT 6 . . . 1
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
11
3
12
LSB IN
10
LSB OUT
Figure A-5 SPI Master Timing (CPHA = 0)
115
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