MC9S12H256 Datasheet, PDF (58/130 Pages) Motorola, Inc – Device User Guide

MC9S12H256 Device User Gui^Fde^r—^eeV^s01^c.1^a8 ^{le Semiconductor, Inc.}
2.2 Signal Properties Summary
Table 2-1 summarizes all pin functions.
NOTE: Bold entries determine pins not available on 112-pin LQFP.
Table 2-1 Signal Properties
Pin Name Pin Name Pin Name Pin Name Powered
Function 1 Function 2 Function 3 Function 4 by
EXTAL
XTAL
RESET
TEST
XFC
BKGD
PAD[7:0]
PAD[15:8]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH[7:0]
—
—
—
—
—
TAGHI
AN[7:0]
AN[15:8]
FP[15:8]
FP[7:0]
FP22
IPIPE1
IPIPE0
ECLK
FP21
FP20
IRQ
XIRQ
KWH[7:0]
—
—
—
—
—
MODC
—
—
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
XCLKS
MODB
MODA
—
LSTRB
R/W
—
—
—
PJ[3:0] KWJ[3:0]
—
—
—
—
—
—
—
—
—
—
—
NOACC
—
—
—
TAGLO
—
—
—
—
—
VDDPLL
VDDPLL
VDDX2
VDDX2
VDDPLL
VDDX2
VDDA
VDDA
VDDX1
VDDX1
VDDX1
VDDX2
VDDX2
VDDX2
VDDX1
VDDX1
VDDX2
VDDX2
VDDM
VDDX1
PK7
FP23
ECS
ROMONE VDDX1
PK[3:0]
BP[3:0] XADDR[17:14]
—
PL[3:0]
FP[19:16]
—
—
PL[7:4] FP[31:28]
—
—
VDDX1
VDDX1
VDDX1
Internal Pull
Resistor
CTRL
Reset
State
Description
Oscillator Pins
None
None External Reset Pin
Test Input
PLL Loop Filter
Always
Up
Up
Background Debug, Tag High, Mode
Pin
Port AD Inputs, Analog Inputs (ATD)
None
None _{Port AD Inputs, Analog Inputs}
(ATD)
PUCR/
PUPAE
Down Port A I/O, Multiplexed Address/Data
PUCR/
PUPBE
Down Port B I/O, Multiplexed Address/Data
PUCR/
PUPEE
Down
Port E I/O, Access, Clock Select,
LCD driver
While RESET pin is ^{Port E I/O, Pipe Status, Mode Input}
low: Down
Port E I/O, Pipe Status, Mode Input
Port E I/O, Bus Clock Output
PUCR/
PUPEE
Mode de- Port E I/O, LCD driver, Byte Strobe,
pendent Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Up
Port E Input, Non Maskable Interrupt
PERH/
PPSH
Disabled Port H I/O, Interrupts
PERJ/
PPSJ
Disabled Port J I/O, Interrupts
PUCR/
PUPKE
Down
Port K I/O, Emulation Chip Select,
ROM On Enable
Port K I/O, LCD driver, Extended
Addresses
PERL/
PPSL
Port L I/O, LCD drivers
Down
Port L I/O, LCD drivers
58
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