MC88921 Datasheet, PDF (8/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88921
The tPD spec includes the full temperature range from 0°C
to 70°C and the full VCC range from 4.75V to 5.25V. If the
∆T and ∆VCC is a given system are less than the
specification limits, the tPD spec window will be reduced.
The tPD window for a given ∆T and ∆VCC is given by the
following regression formula:
TBD
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 7 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1a. All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1b. The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will make the 88921 PLL
insensitive to voltage transients from the system digital
VCC supply and ground planes. This filter will typically
ensure that a 100mV step deviation on the digital VCC
supply will cause no more than a 100ps phase deviation
on the 88921 outputs. A 250mV step deviation on VCC
using the recommended filter values will cause no more
than a 250ps phase deviation; if a 25µF bypass capacitor
is used (instead of 10µF) a 250mV VCC step will cause no
more than a 100ps phase deviation.
If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88921’s digital VCC supply. The
purpose of the bypass filtering scheme shown in Figure 7
is to give the 88921 additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.
1c. There are no special requirements set forth for the loop
filter resistors (1M and 330Ω). The loop filter capacitor
(0.1uF) can be a ceramic chip capacitor, the same as a
standard bypass capacitor.
1d. The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3µA).
2. In addition to the bypass capacitors used in the analog
filter of Figure 7, there should be a 0.1µF bypass
capacitor between each of the other (digital) four VCC
pins and the board ground plane. This will reduce output
switching noise caused by the 88921 outputs, in addition
to reducing potential for noise in the ‘analog’ section of
the chip. These bypass capacitors should also be tied as
close to the 88921 package as possible.
10µF LOW
FREQ BIAS
0.1µF HIGH
FREQ BIAS
BOARD VCC
47Ω
5 ANALOG VCC
1MΩ
330Ω
ANALOG LOOP FILTER/VCO
6 RC1
SECTION OF THE MC88921
20–PIN SOIC PACKAGE (NOT
0.1µF (LOOP
DRAWN TO SCALE)
FILTER CAP)
7 ANALOG GND
47Ω
BOARD GND
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE-
LINES IS ALL THAT IS NECESSARY TO USE THE MC88921 IN A NORMAL
DIGITAL ENVIRONMENT.
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88921
MOTOROLA
8
TIMING SOLUTIONS
BR1333 — REV 5