MC88921 Datasheet, PDF (5/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88921
AC CHARACTERISTICS (TA = –40°C to 85°C; VCC = 5.0V ± 5%)
Symbol
tRISE/FALL¹
All Outputs
tRISE/FALL¹
2X_Q Output
tpulse _width(a)¹
(Q0, Q1, Q2, Q3)
tpulse _width(b)¹
(2X_Q Output)
tPD^1,4
SYNC – Q/2
Parameter
Rise/Fall Time, All Outputs into 50Ω
Load
Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3
Output Pulse Width
Q0, Q1, Q2, Q3 at VCC/2
Output Pulse Width
2X_Q at VCC/2
SYNC Input to Q Output Delay
(Measured at SYNC and Q/2 Pins)
tSKEWr^1,2
(Rising)
tSKEWf^1,2
(Falling)
tSKEWall^1,2
tLOCK³
Output–to–Output Skew
Between Outputs Q0–Q3
(Rising Edge Only)
Output–to–Output Skew
Between Outputs Q0–Q3
(Falling Edge Only)
Output–to–Output Skew
2X_Q, Q0–Q3 Rising
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
Minimum
0.3
0.5
0.5tcycle – 0.5⁵
0.5tcycle – 0.5⁵
–0.75
+1.25 ⁷
—
—
—
1
Maximum
Unit
Condition
1.6
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
1.6
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
0.5tcycle + 0.5⁵ ns 50Ω Load Terminated to
VCC/2 (See Application
Note 3)
0.5tcycle + 0.5⁵ ns 50Ω Load Terminated to
VCC/2 (See Application
Note 3)
–0.15
+3.25 ⁷
ns With 1MΩ From RC1
to An VCC
(See Application Note 2)
ns With 1MΩ From RC1
to An GND
(See Application Note 2)
500
ps Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
1.0
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
1.0
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
10
ms
tPHL MR – Q
Propagation Delay,
1.5
MR to Any Output (High–Low)
tREC, MR to
Reset Recovery Time rising MR edge
9
SYNC⁶
to falling SYNC edge
13.5
ns Into a 50Ω Load
Terminated to VCC/2
—
ns
tREC, MR to
Recovery Time for Outputs 2X_Q, Q0,
—
3 Clock Cycles ns
Normal Operation Q1 to Return to Normal PLL Operation
(Q Frequency)
tW, MR LOW⁶
Minimum Pulse Width, MR input Low
5
—
ns
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF.
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Refer to Application Note 3 to translate signals to a 1.5V threshold.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
TIMING SOLUTIONS
5
BR1333 — REV 5
MOTOROLA