MC88921 Datasheet, PDF (7/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

88921
2X_Q
OUTPUT
Zo (CLOCK
Rs
TRACE)
Rs = Zo – 7Ω
68040
P–CLOC
K
RP _INPUT
RP = 1.5Zo
Figure 3. MC68040 P–Clock Input Termination Scheme
MC88921
16.5MHz
CRYSTAL
OSCILLATOR
SYNC
MR
PLL_EN
2X_Q
Q0
Q1
Q2
Q3
66MHz P–CLOCK OUT-
PUT
33MHz
B–CLOCK
AND SYSTEM
OUTPUTS
Figure 4. Logical Representation of the MC88921 With Input/Output Frequency Relationships
SYNC Input
tSKEWall
Q0–Q3 Outputs
tSKEWf
tCYCLE SYNC Input
tSKEWr
tSKEWf
tSKEWr
2X_Q Output
Figure 5. Output/Input Switching Waveforms and Timing Relationships
Timing Notes
1. The MC88921 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
‘windows’, not as a ± deviation around a center point.
TIMING SOLUTIONS
7
BR1333 — REV 5
MOTOROLA