MC88921 Datasheet, PDF (4/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88921
LOCK
SYNC1
LOCK INDICATOR
RC1
PFD
CH
PUMP
VCO
PLL_EN
01
POWER–ON
÷2
RESET
MR
D
Q
R
D
Q
R
D
Q
R
D
Q
Q
R
2X_Q
Q0
Q1
Q2
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
D
Q
Q3
R
FBSEL
0
1
D
Q
Q/2
R
Figure 1. MC88921 Logic Block Diagram
FREQUENCY SPECIFICATIONS (TA = –40°C to 85°C; VCC = 5.0V ± 5%)
Symbol
Parameter
Guaranteed Minimum
Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output
66
Fmax (‘Q’)
Maximum Operating Frequency,
33
Q0–Q3 Outputs
1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF.
Unit
MHz
MHz
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5