MC88921 Datasheet, PDF (2/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88921
Power–Down Mode Functionality
The MC88921 has a special feature
designed in to allow the processor clock
inputs to be reset for total processor
power–down, and then to return to
phase–locked operation very quickly when
the processor is powered–up again.
The MR pin resets outputs 2X_Q, Q0
and Q1 only leaving the other outputs
operational for other system activity. When
MR is negated, all outputs will be operating
normally within 3 clock cycles.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
CIN
CPD
PD1
PD2
Input Capacitance
Power Dissipation Capacitance
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
Q3 1
VCC 2
MR 3
PLL_EN 4
VCC(AN) 5
RC1 6
GND(AN) 7
SYNC 8
GND 9
Q0 10
20 GND
19 2X_Q
18 Q/2
17 VCC
16 Q2
15 GND
14 LOCK
13 FBSEL
12 Q1
11 VCC
Pinout: 20–Lead Wide SOIC Package (Top View)
Value Typ
Unit
4.5
pF
40
pF
15mW/Output
mW
90mW/Device
37.5mW/Output
mW
225mW/Device
Test Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
T = 25°C
VCC = 5.0V
T = 25°C
MAXIMUM RATINGS*
Symbol
Parameter
Limits
Unit
VCC, AVCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage Referenced to GND
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, Per Pin
DC Output Sink/Source Current, Per Pin
DC VCC or GND Current Per Output Pin
Storage Temperature
–0.5 to 7.0
V
–0.5 to VCC +0.5
V
–0.5 to VCC +0.5
V
±20
mA
±50
mA
±50
mA
–65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 5