MMDF2C02E Datasheet, PDF (7/12 Pages) ON Semiconductor – Power MOSFET

MMDF2C02E
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R_θJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
N–Channel
100
VGS = 20 V
SINGLE PULSE
10 ^{TC = 25°C}
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max.
100 µs ^{10 µs}
10 ms
1
dc
P–Channel
100
VGS = 20 V
SINGLE PULSE
10 ^{TC = 25°C}
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max.
100 µs ^{10 µs}
10 ms
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
280
I pk = 9 A
240
200
160
120
80
40
0
25
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 9. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
280
I pk = 7 A
240
200
160
120
80
40
0
25
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 9. Maximum Avalanche Energy versus
Starting Junction Temperature
Motorola TMOS Power MOSFET Transistor Device Data
7