MMDF2C02E Datasheet, PDF (1/12 Pages) ON Semiconductor – Power MOSFET

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2C02E/D
™ Designer's Data Sheet
Medium Power Surface Mount Products
Complementary TMOS
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
®
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
D
N–Channel
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the G
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
S
D
P–Channel
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Rating
MMDF2C02E
COMPLEMENTARY
DUAL TMOS POWER FET
2.5 AMPERES
25 VOLTS
RDS(on) = 0.100 OHM
(N–CHANNEL)
RDS(on) = 0.25 OHM
(P–CHANNEL)
CASE 751–05, Style 14
SO–8
N–Source
N–Gate
P–Source
P–Gate
18
27
36
45
Top View
N–Drain
N–Drain
P–Drain
P–Drain
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage
Drain Current — Continuous
— Pulsed
N–Channel
P–Channel
N–Channel
P–Channel
VDSS
VGS
ID
IDM
25
Vdc
± 20
Vdc
3.6
Adc
2.5
18
13
Operating and Storage Temperature Range
Total Power Dissipation @ TA= 25°C ⁽²⁾
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25 Ω)
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient ⁽²⁾
N–Channel
P–Channel
Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds.
TJ and Tstg
PD
EAS
R_θJA
TL
– 55 to 150
2.0
245
245
62.5
260
°C
Watts
mJ
°C/W
°C
DEVICE MARKING
F2C02
(1) Negative signs for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF2C02ER2
13″
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 5
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