DSP56309UM Datasheet, PDF (60/424 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor, Inc.
Signal/Connection Descriptions
Interrupt and Mode Control
2.7 INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chipÕs operating mode as it comes out
of hardware reset. After RESET is deasserted, these inputs are hardware interrupt
request lines.
Table 2-9 Interrupt and Mode Control
Signal Name
Type
State
During
Reset
Signal Description
RESET
MODA
Input Input
Input Input
ResetÑRESET is an active-low, Schmitt-trigger
input. Deassertion of RESET is internally
synchronized to the clock out (CLKOUT). When
asserted, the chip is placed in the Reset state and
the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input
(such as a capacitor charging) to reset the chip
reliably. If RESET is deasserted synchronous to
CLKOUT, exact start-up timing is guaranteed,
allowing multiple processors to start
synchronously and operate together in lock-step.
When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET
signal must be asserted after power up.
Mode Select AÑMODA is an active-low
Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into the OMR when the RESET signal is
deasserted.
IRQA
External Interrupt Request AÑAfter reset, this
signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQA to exit the wait state. If the
processor is in the stop standby state and IRQA is
asserted, the processor exits the stop state.
2-14
DSP56309UM/D
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