DSP56309UM Datasheet, PDF (109/424 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

4.3.4
Freescale Semiconductor, Inc.
Core Configuration
Bootstrap Program
Mode 9: Boot from Byte-Wide External Memory
Mode MODD MODC MODB MODA
Reset
Vector
Description
9
1
0
0
1
$FF0000 Boot from byte-wide
memory (at $D00000)
The bootstrap program loads instructions through Port A from external byte-wide
memory, starting at P:$D00000. The SRAM memory access type is selected by the values
in address attribute register 1 (AAR1). Thirty-one wait states are inserted between each
memory access. Address $D00000 is reflected as address $00000 on Port A signals
HA0-HA17.
4.3.5 Mode A: Boot from SCI
Mode MODD MODC MODB MODA
Reset
Vector
Description
A
1
0
1
0
$FF0000 Boot through SCI
Instructions are loaded through the SCI. The bootstrap program sets the SCI to operate
in 10-bit asynchronous mode, with one start bit, eight data bits, one stop bit and no
parity. Data is received in this order; start bit, eight data bits (LSB first), and one stop bit.
Data is aligned in the SCI receive data register with the LSB of the least significant byte
of the received data appearing at bit 0. The user must provide an external clock source
with a frequency at least 16 times the transmission data rate. Each byte received by the
SCI is echoed back through the SCI transmitter to the external transmitter.
4.3.6 Mode B: Reserved
Mode MODD MODC MODB MODA
Reset
Vector
Description
B
1
0
1
1
$FF0000 Reserved
This mode is reserved for future use.
MOTOROLA
DSP56309UM/D
4-7
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